COG (chip on glass) refers to a technology of flip chip. Metal bumps of a driver IC are mounted directly to an indium tin oxide (ITO) layer that is attached on a plurality of bonding pads fabricated on a same transparent substrate of an LCD panel, using an anisotropic conductive film (ACF) as a vehicle for bonding the chip to the transparent substrate.
Referring to FIG. 1, a cross-sectional view of an LCD structure is shown. A silicon-based island 14 with a source region 14s and a drain region 14d formed in respective ends is disposed on pixel area of a glass substrate 12. Between the source region 14s and drain region 14d sandwiched a channel region 14c. A gate oxide film 16 is formed on the glass substrate 12 and covers the silicon-based island 14. A gate 18 is arranged on a portion of the gate oxide film 16 over the channel region 14c. The gate 18, gate oxide film 16 and silicon-based island 14 comprise a thin film transistor (TFT).
An interlayer dielectric (ILD) layer 20 is disposed on the glass substrate 12 and covers the TFT. First contact holes 21 are formed in the ILD layer 20 and gate oxide film 16 to expose portions of upper surfaces of the source region 14s and drain region 14d, respectively. A plurality of interconnections 22 and bonding pads 23 are formed simultaneously in the respective first contact holes 21 over pixel area of the glass substrate 12 and on the ILD layer 20 over marginal area of the glass substrate 12. The interconnections 22 are formed to electrically connect to the source region 14s and drain region 14d, whereas the bonding pads 23 are provided for metal bumps of COG.
A passivation layer 24 is formed on the ILD layer 20 and covers the interconnections 22 and bonding pads 23. A second contact hole 25 and a plurality of bonding openings 31 are formed simultaneously in the passivation layer 24 over pixel area and marginal area of the glass substrate 12, respectively. The second contact hole 25 is formed to expose a portion of upper surface of the interconnection 22 that is in direct contact with the source region 14s. The bonding openings 31 are formed to expose upper surfaces of the bonding pads 23. A planarizing film 28 is formed on the passivation layer 24 over pixel area of the glass substrate 12 and fills the second contact hole 25.
A third contact hole 30 is fabricated in the planarizing film 28. Still referring to FIG. 1, the third contact hole 30 is located in the second contact hole 25. It is noted that side walls of the second contact hole 25 is completely covered by the planarizing film 280, whereas a portion of the bottom surface of the second contact hole 25 is exposed.
Referring to FIG. 2, a pixel electrode 32 is attached on surfaces of the planarizing film 28, the third contact hole 30 and the bonding pads 23.
FIGS. 3 to 5 show steps of manufacturing the LCD structure mentioned above. Referring to FIG. 3, a silicon-based island 14 is defined on pixel area of a glass substrate 12. Next, both ends of the silicon-based island 14 are doped to form a source region 14s and a drain region 14d therein, respectively. A gate oxide film 16 is then formed by chemical vapor deposition (CVD) on the glass substrate 12 and covers the silicon-based island 14. A gate 18 is formed on a portion of the gate oxide film 16 over the region 14c. The gate 18, gate oxide film 16 and silicon-based island 14 comprise a TFT.
Referring to FIG. 4, an ILD layer 20 is deposited on the glass substrate 12 and covers the TFT. Next, a plurality of first contact holes 21 are formed in the ILD layer 20 and gate oxide film 16 to expose portions of upper surfaces of the source region 14s and drain region 14d, respectively. A conductive layer is then sputtered on the ILD layer 20 and fills the first contact holes 21. Thereafter, the conductive layer is patterned to form a plurality of interconnections 22 and bonding pads 23 simultaneously in the first contact holes 21 over pixel area of the glass substrate 12 and on the ILD layer 20 over marginal area of the glass substrate 12, respectively. The interconnections 22 are used to electrically connect to the source region 14s and drain region 14d, whereas the bonding pads 23 are provided for metal bumps of the COG.
Referring to FIG. 5, a passivation layer 24 is deposited on the ILD layer 20, covering the interconnecting layer 22 and bonding pads 23. Then, a second contact hole 25 is formed in the passivation layer 24 over the interconnecting layer 22 directly contact with the source region 14s to expose a part of upper surface of the interconnecting layer 22. At the same time, a plurality of bonding openings 31 are formed in the passivation layer 24 over the bonding pads 23 to expose upper surfaces thereof. Thereafter, a planarizing film 28 is fabricated on the passivation layer 24 over pixel area of the glass substrate 12.
Still referring to FIG. 5, a third contact hole 30 is formed in the planarizing film 28 to expose a part of bottom surface of the second contact hole 25. It is noted that side walls of the second contact hole 25 are completely covered by the planarizing film 28. In one preferred embodiment, the third contact hole 30 is formed by development, etching or the combination thereof.
Referring back to FIG. 2, a pixel electrode 32 is formed on the planarizing film 28 and bonding pads 23, and covers the surface of the third contact hole 30, simultaneously.
In the prior art, the passivation layer 24 can be substituted for the planarizing film 28, thus saving procedures of forming the passivation layer 24 and the second contact hole 25. However, when metal bumps of COG are in bad contact with the bonding pads 23 insulated by the planarizing film 28, it is necessary to remove the COG from the bonding pads 23 and clean the bonding pads with a solution. After the cleaning, metal bumps of the COG are re-mounted onto the pixel electrode 32 over the bonding pads 23. These steps are called re-work process.
In the re-work process, the planarizing film 28 used to insulate the bonding pads 23 tends to react with the solution. Therefore, the occurrence of the planarizing film 28 peeling off from the ILD layer 16 is elevated.